The present invention relates generally to a high thermal performance and high reliability flip chip package assembly and more specifically to a high thermal performance and high reliability flip chip package assembly having a retainer frame with a demountable heat spreader.
As minimum feature sizes of integrated circuits (IC) continue to shrink and IC system performance continues to increase, the amount of waste heat generated by an IC plays a major role in determining IC reliability and the cost of packaging used to house the IC. Due to the decrease in the feature sizes more components are fabricated in the IC thereby increasing the amount of waste heat generated. Increases in system performance made possible by reduced feature sizes have given rise to higher system clock speeds. Those higher clock speeds also contribute to the waste heat generated by the IC. If the waste heat is not adequately dissipated the IC will destroy itself or the IC will later fail in an end product application such as a notebook PC, for example. The trend towards systems on a chip further exacerbates the amount of waste heat that must be removed from an IC because the heat dissipated by several IC that would normally be in separate packages are integrated into a single IC housed in one package. Removing the waste heat from an IC die often requires expensive packaging and costly manufacturing processes. As a result, package cost is a major component of the overall cost of the IC.
A high performance IC, such as a system on a chip, tends to have a high input/output interconnect count (IO). Because of the high IO count it is not always possible or desirable to position IO pads of an IC die along the edges of the die. Instead, the IO pads are arranged in an array on an interconnect side of the die. This configuration is called an area array flip chip. The flip chip is mounted on a substrate such as a multi-layer ceramic, for example. The substrate has a matching array of bonding pads. Solder bumps are placed on the IO pads of the die and the IO pads are soldered to the matching array of bonding pads by reflowing the solder bumps.
One disadvantage of the flip chip is that the backside of the die (the side opposite the interconnect side) is exposed and is not in thermal communication with the substrate. Unlike traditional wire bond mounting techniques where the backside is mechanically and thermally connected to a heat spreader that forms part of the substrate, the flip chip construction requires a separate heat spreader to be mounted on the backside. Mounting the heat spreader on the backside creates mechanical loads on the die, solder bumps, and the substrate. Those mechanical loads can cause the solder bumps to fail resulting in a defective IC. Additionally, the waste heat generated by the IC can also cause the IC to fail due to thermal mismatch between the lid, the die, the substrate, and the solder bumps.
Moreover, the heat spreader must often serve as the lid for the IC package. Subsequently, the lid must be attached to the substrate and the area between the substrate, the die, and the lid must be filled with a material that seals the area. This adds to the cost of the IC and introduces another possible failure mode for the IC due to thermal mismatch between the material used to fill the area and the die, the lid, the solder bumps, and the substrate. Additionally, another thermal mismatch occurs when the substrate containing the IC is mounted to a PC board in order for the IC to communicate with external circuits mounted on the PC board. In order to dissipate the waste heat from high performance IC, ceramic, is typically used for the substrate material. Ceramic is the material of choice due to its closer match of coefficient of thermal expansion with that of silicon, and its high thermal conductivity and mechanical strength over those of laminate materials. Typically, the ceramic substrate has secondary IO connections that are surface mounted to the PC board using a reflow solder process. However, during system operation when the IC is powered up or powered down, there is a thermomechanical interaction between the IC package assembly and the PC board due to differences in coefficients of thermal expansion of the PC board and the substrate. Mechanical stress created by the thermal mismatch can cause the secondary IO connections to fail. Furthermore, the thermomechanical interaction introduces additional mechanical stresses between the lid, the substrate, and the solder bumps that can also result in failure of the IC.
Therefore, there is a need for an IC package assembly that is low in cost, does not require expensive package materials, has high power dissipation for high-performance IC's, eliminates the need to attach the lid to the substrate, does not require a fill material between the lid and the IC die, improves reliability, and reduces thermomechanical stress between the lid and the die.